1. Field of the Invention
The present invention generally relates to data driven type information processors performing processing when all the data required for an action are available, and more particularly, to a data driven type information processor having an improved initialization function.
2. Description of the Related Art
In fields such as image processing and various simulations, there is a need for improvement of performance of an information processor. One system for improving the processing performance of the information processor is parallel processing. The data driven type information processor is of an architecture employing the parallel processing system.
In a conventional yon Neumann type information processor, various instructions are prestored in a memory as programs. By a program counter specifying addresses of the memory sequentially, individual instructions are read out in a sequence to be executed.
On the other hand, a data driven type information processor employing the parallel processing system is one kind of non Neumann type information processors not having a concept of a sequential execution of instructions by the program counter. The data driven type information processor operates according to a simple rule that "when all the data needed for an action are available and hardware resources such as an operation unit required for the action are assigned thereto, the action is carried out." Therefore, the data driven type information processor can perform operations associated with a plurality of instructions simultaneously according to a flow of data, that is, can execute data flow programs in parallel. With the data driven type information processor, parallel processing of programs is considered to substantially shorten a time required for operation.
Note that a state where all the data needed for an action are available is called "firing". To match input data in order to provide data is called "matching control" or "firing control".
Input/output of data to/from the data driven type information processor and transmission of data within the data driven type information processor are carried out in a form of a data packet. A data packet includes operand data, instruction information, destination information, and generation information, for example.
The operand data is data to be processed. The instruction information specifies the processing content. The destination information specifies a destination to which a data packet is to be sent. The generation information identifies the same set of data when firing control is made to a plurality of sets of data.
FIG. 1 is a block configuration diagram of a general data driven type information processor. A data driven type information processor 91 (hereinafter simply referred to as a "processor 91") matches two operand data if required when carrying out processing. Processor 91 includes a junction unit 901, a firing control unit 902 making matching control, an operation unit 905, a data memory 906, a program storage unit 907, and a branch unit 909.
Junction unit 901 merges input paths of data packets from the outside and the inside of processor 91, and sends the applied data packets to firing control unit 903.
When processing specified by instruction information included in a data packet requires two operand data, firing control unit 903 matches operand data included in two different data packets. Firing control unit 903 includes a memory (not shown) for matching the operand data. As soon as two operand data required are provided, firing control unit 903 stores the two operand data in one data packet, and sends the data packet to operation unit 905.
Operation unit 905 performs arithmetic operation, logic operation, or the like based on the instruction information to the operand data. Data memory 906 stores data for operation (hereinafter referred to as "operation information") which the operation unit 905 uses to perform operation. Operation unit 905 reads out operation information from data memory 906, or writes data in data memory 906 as required. Operation unit 905 stores the operation result in a data packet as operand data, and sends the data packet to program storage unit 907.
Program storage unit 907 prestores a plurality of data flow programs. In this specification, a data flow program refers to an instruction for specifying processing carried out at one node and information associated therewith, when the entire processing is represented in a data flow graph. Program storage unit 907 provides a corresponding data flow program based on destination information included in the data packet. The data flow program includes the next instruction information and the next destination information. Program storage unit 907 stores the read instruction information and destination information as the next instruction information and the next destination information in a data packet, and sends the data packet to branch unit 909.
Branch unit 909 branches an output path of the data packets into a path to the outside of processor 91 or to the inside of processor 91. More specifically, based on destination information of the data packet, branch unit 909 determines whether the data packet should be sent to the outside of processor 91 or to junction unit 901 in processor 91.
An initialization unit 911, an initialization information memory 912, and a reset signal input unit 913 are provided external to processor 91 as peripheral devices. Initialization unit 911 generates a data packet for initializing (hereinafter referred to as an "initialization data packet") processor 91 based on initialization information read out from initialization information memory 912, and applies the data packet to processor 91. Reset signal input unit 913 includes a switch such as a push button. Reset signal input unit 913 is connected to junction unit 901, firing control unit 903, operation unit 905, program storage unit 907, and branch unit 909 within processor 91 through a signal line 915.
Immediately after power-on, processor 91 carries out initialization processor for entering a state where processor 91 itself operates properly. When changing the processing content of processor 91, the user forces processor 91 to carry out initialization processing in order to download another data flow program in program storage unit 907 for example. Description will now be given of initialization of the data driven type information processor.
FIGS. 2 (a) and 2 (b) are schematic diagrams showing transition of states of the data driven type information processor. In the following description, the state of each unit included in the data driven type information processor falls into four states of (1) Unknown (an indefinite state immediately after power-on), (2) Cold (a state where reset processing (Reset) is carried out in the Unknown state), (3) Warm (a state where initialization processing (Initialize) is performed in the Cold state), and (4) Hot (a state where a data packet is applied in the Warm state, and processing is being executed (Execute)).
Reset clears data stored in a register, an internal memory, or the like included in each unit. If there is a program being executed, the program is stopped. If reset processing is performed in any state of Unknown, Warm, or Hot, the state transitions to the Cold state. Initialization means to set data in a register, an internal memory, or the like, and to bring each unit to a state where normal processing is carried out upon application of a data packet. When each unit is in the Unknown state or the Cold state, proper processing is not carried out generally, although a data packet can be input to the data driven type information processor.
Firing control unit 903, operation unit 905, and program storage unit 907 of processor 91 shown in FIG. 1 transition among four states of Unknown, Cold, Warm, and Hot, as shown in FIG. 2 (a). On the other hand, for junction unit 901 and branch unit 909, the Cold state and the Warm state are not separate. As shown in FIG. 2 (b), junction unit 901 and branch unit 909 transitions among three states of Unknown, Cold/Warm, and Hot. Junction unit 901 and branch unit 909 do not have to prestore data needed for the operations in internal memories. Therefore, it is not necessary to perform initialization processing to these units. If reset processing is carried out, these units operate properly in response to application of a data packet.
When processor 91 is to be initialized, an initialization data packet is applied to processor 91 with initialization unit 911 external to processor 91. When initialization processing is carried out to the entire processor 91, that is, to firing control unit 903, operation unit 905, and program storage unit 907, it is necessary to reset internal circuitry of processor 91 before application of an initialization data packet, and to bring each unit in any state of Unknown, Cold, Warm, Cold/Warm or Hot to the Cold state. This is because a remaining program or data in processor 91 might cause processor 91 to abnormally stop or run out of control. It should be noted that junction unit 901 and branch unit 909 do not have to be initialized, as described before.
The operator applies a reset signal to processor 91 with reset signal input unit 913 to reset each unit. The reset signal is applied to each unit through signal line 915. Each unit resets itself in response to the reset signal, and enters the Cold state or the Cold/Warm state. After sufficient time for the entire processor 91 to enter the Cold state or the Cold/Warm state, the operator starts initialization unit 911, applies an initialization data packet to processor 91, and causes initialization unit 911 to perform initialization processing.
The initialization data packet applied to processor 91 is sent to firing control unit 903, operation unit 905, and program storage unit 907 in this order via junction unit 901. If there is no instruction information in the sent initialization data packet which is to initialize themselves, firing control unit 903, operation unit 905, and program storage unit 907 send the initialization data packet to the next unit. If there is instruction information in the received initialization data packet which is to initialize themselves, firing control unit 903, operation unit 905, and program storage unit 907 initialize themselves according to the instruction information. Each of firing control unit 903, operation unit 905, and program storage unit 907 discards the initialization data packet after initialization processing is complete. Accordingly, when the initialization data packet applied to processor 91 arrives at a corresponding functional unit, the unit is initialized.
On the other hand, if initialization is performed to change only part of processor 91, for example, part of the data flow programs of program storage unit 907, reset processing is not required. The operator causes initialization unit 911 to generate an initialization data packet for initializing part of processor 91, and applies the initialization data packet to processor 91. When the applied initialization data packet arrives at a corresponding functional unit, for example, program storage unit 907, the functional unit is initialized.
Note that, when the data driven type information processor is initialized, a peripheral device for generating an initialization data packet must be provided as an initialization unit, as shown in the above described configuration example of processor 91. This is because the data driven type information processor accepts only a data packet as input. The initialization unit is generally configured of an information processor such as a computer system. Therefore, using the initialization unit as a peripheral device complicates the configuration of a system, a device, or the like in which the data driven type information processor is incorporated.
As a means for eliminating such a disadvantage, the following device may be contemplated.
FIG. 3 is a block configuration diagram of a data driven type information processor in which an initialization unit is incorporated. Units having the same functions as those of FIG. 1 have the same reference characters and the same names. Therefore, the detailed description thereof will not be repeated here as far as not required.
A processor 92 includes an initialization unit 921 and an initialization information memory 923 in addition to junction unit 901, firing control unit 903, operation unit 905, data memory 906, program storage unit 907, and branch unit 909. Reset signal input unit 913, a start address input unit 925, and an address number input unit 927 are provided external to processor 92.
Reset signal input unit 913 is connected to junction unit 901, firing control unit 903, operation unit 905, program storage unit 907, and branch unit 909 through a signal line 929 and a signal line 930. Start address input unit 925 is connected to initialization unit 921 through a signal line 933. Address number input unit 927 is connected to initialization unit 921 through a signal line 935. Initialization unit 921 is connected to initialization information memory 923 through a signal line 939 and a signal line 937.
Signal line 937 transmits an access signal and a read address for reading out initialization information from initialization unit 921 to initialization information memory 923. Signal line 939 transmits read initialization information from initialization information memory 923 to initialization unit 921.
An initialization data packet provided from initialization unit 921 is applied to junction unit 901 through signal lines 941.
FIG. 4 is a block configuration diagram of initialization unit 921. Initialization unit 921 includes a control unit 951, a counter unit 953, a comparison unit 955, and a data packet generation unit 957. A signal line 963 and a signal line 965 is branched from signal line 929 transmitting a reset signal. A signal line 929 is connected to control unit 951. Signal line 963 is connected to data packet generation unit 957. Signal line 965 is connected to counter unit 953 and comparison unit 955.
Control unit 951 generates a clock signal for generating an initialization data packet in response to a reset signal applied through signal line 929. The clock signal is applied to counter unit 953 through signal line 967. Counter unit 953 counts the number of pulses of the clock signal. First, counter unit 953 resets the count value to "0" in response to the reset signal. Then, counter unit 953 counts up the count value in response to the clock signal one by one, sends the count value to data packet generation unit 957 and comparison unit 955 through signal line 969 and signal line 971.
Data packet generation unit 957 adds a start address received from start address input unit 925 (cf. FIG. 3) through signal line 933 and a count value received from counter unit 953 through signal line 969, and generates a read address for reading out initialization information of initialization information memory 923. Data packet generation unit 957 sends the access signal and the read address to initialization information memory 923 through a signal line 939. The read initialization information is sent to data packet generation unit 957 from initialization information memory 923 through a signal line 937.
Data packet generation unit 957 generates an initialization data packet based on the read initialization information. The generated initialization data packet is sent to junction unit 901 through signal lines 941. The generation of an initialization data packet is continued as far as a clock signal is provided from control unit 951.
On the other hand, comparison unit 955 compares the count value sent from counter unit 953 with the address number sent from address number input unit 927 through signal line 935. When the count value is equal to the address number, comparison unit 955 sends a signal indicating that the count value is equal to the address number to control unit 951 through a signal line 973.
Control unit 951 stops generation of a clock signal in response to the signal sent from comparison unit 955. As a result, generation of an initialization data packet is complete.
In initializing processor 92, the operator sets a read start address and a read address number of initialization information with start address input unit 925 and address number input unit 927, and applies a reset signal to processor 92 with reset signal input unit 913 for a prescribed time.
In response to the reset signal, processor 92 is brought to the Cold state. After a prescribed time, initialization unit 921 starts the above described generation of an initialization data packet in response to the reset signal switching from an ON state to an OFF state (termination of the reset signal). Initialization of processor 92 is thus triggered by end of the reset signal.
Such a processor as described above is more advantageous than a conventional processor in that the former does not require a separate information processor. However, this processor has a following problem to be solved.
More specifically, processor 92 incorporates initialization unit 921 and initialization information memory 923 therein. Therefore, the configuration of the processor becomes complicated, and the size of the processor is larger. Since initialization unit 921 starts by being triggered by termination of the reset signal, the operator must input the reset signal to processor 92 when initializing the processor. Even if it is desired to initialize processor 92 without stopping the operation as is the case where part of the data flow programs stored in program storage unit 907 is changed, processor 92 is brought to the Cold state and stopped in response to input of the reset signal.